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ISL55036
Data Sheet September 11, 2008 FN6640.1
400MHz Slew Rate Enhanced Rail-to-Rail Output Gain Block
The ISL55036 is a hex, rail-to-rail output, fixed gain amplifier (G = 4) with a -3dB bandwidth of 400MHz and slew rate of 2500V/s into a 150 load. The ISL55036 features single supply operation over a voltage range of 3VDC to 5.5VDC. The inputs are capable of sensing ground with an output swing of VCC - 0.3V into a 150 load tied to V+/2. The part includes a fast-acting global disable/power-down circuit. The ISL55036 is available in a 24 Ld TQFN package. Operation is specified over the -40C to +85C temperature range.
Features
* 400MHz -3dB Bandwidth * 2500V/s Typical Slew Rate, RL = 150 * Supplies from 3V to 5.5V * Rail-to-Rail Output (RL = 1k) * Input Ground Sensing * Fast 25ns Disable * Low Cost * Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER ISL55036IRTZ PART MARKING 55036 IRTZ PACKAGE (Pb-free) 24 Ld TQFN 24 Ld TQFN PKG. DWG. # L24.4x5C L24.4x5C
Applications
* Video RGB Line Driver * LCD Based Projectors Pixel Control
ISL55036IRTZ-T13* 55036 IRTZ
Pinout
ISL55036 24 LD TQFN TOP VIEW
V+ (1, 2, 3) EN(1, 2, 3) V+ OUT(1,2,3) 21
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
IN+_2
0.80 0.75
24 1 2 3 4 5
23
-+
22
20 19 OUT_2 18 17 OUT_3 GND_OUT(1, 2, 3) GND_PWR(1, 2, 3) V+_OUT(4,5,6) OUT_4 OUT_5
GND_IN(1, 2, 3) EN(4, 5, 6)
SMALL SIGNAL (V) 0.70 0.65 0.60 0.55 0.50 0.45 V+ = 5V AV = +4 RL = 150 CL = 3.0pF VOUT = 250mVP-P
-+
-+
IN+_3
DIE 1
OUT_1 16 15 14 13 12 OUT_6
AV EACH CHANNEL EQUALS +4
IN+_1 V+(4, 5, 6) IN+_4 IN+_5 6
-+
-+
-+
7 8 IN+_6 9 GND_IN(4, 5, 6)
DIE 2
10 GND_PWR(4, 5, 6) 11 GND_OUT(4, 5, 6)
0
5
10
15
20
25
30
35
40
45
50
TIME (ns)
FIGURE 1. SMALL SIGNAL STEP RESPONSE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL55036 Pin Descriptions
24 LD TQFN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 IN+_2 IN+_3 GND_IN(1, 2, 3) EN(4, 5, 6) V+(4, 5, 6) IN+_4 IN+_5 IN+_6 GND_IN(4, 5, 6) GND_PWR(4, 5, 6) GND_OUT(4, 5, 6) OUT_ 6 OUT_ 5 OUT_4 V+_OUT(4, 5, 6) GND_PWR(1, 2, 3) GND_OUT(1, 2, 3) OUT_3 OUT_2 OUT_1 V+_OUT(1, 2, 3) EN(1, 2, 3) V+(1, 2, 3) IN+_1 Thermal Pad PIN NAME EQUIVALENT CIRCUIT Circuit 1 Circuit 1 Circuit 4 Circuit 2 Circuit 5 Circuit 1 Circuit 1 Circuit 1 Circuit 5 Circuit 5 Circuit 3 Circuit 3 Circuit 3 Circuit 3 Circuit 3 Circuit 4 Circuit 3 Circuit 3 Circuit 3 Circuit 3 Circuit 3 Circuit 2 Circuit 4 Circuit 1 Circuit 6 Amplifier 2 non-inverting input Amplifier 3 non-inverting input Common reference input for Amplifiers 1, 2, 3 Enable pin internal pull-down; Logic "1" selects the disabled state; Logic "0" selects the enabled state. Channels 4, 5, 6 Positive power supply for Channels 4, 5, 6. Amplifier 4 non-inverting input Amplifier 5 non-inverting input Amplifier 6 non-inverting input Common reference input for Amplifiers 4, 5, 6 Power supply ground for Channels 4, 5, 6. Output power supply ground for Channels 4, 5, 6. Amplifier 6 output Amplifier 5 output Amplifier 4 output Output power supply for Channels 4, 5, 6. Power supply ground Channels 1, 2, 3. Output power supply ground Channels 1, 2, 3. Amplifier 3 output Amplifier 2 output Amplifier 1 output Output power supply Channels 1, 2, 3. Enable pin internal pull-down; Logic "1" selects the disabled state; Logic "0" selects the enabled state. Channels 1, 2, 3 Positive power supply for Channels 1, 2, 3. Amplifier 1 non-inverting input Thermal heat sink pad makes electrical contact the IC substrate and must be connected to same ground potential as the ground pins.
V+ EN 21k + 1.2V GND_PWR V+_OUT(1, 2, 3) V+_OUT(4, 5, 6) OUT(1, 2, 3) OUT(4, 5, 6) GND_OUT(1, 2, 3) GND_OUT(4, 5, 6) CIRCUIT 2 CIRCUIT 3
DESCRIPTION
V+ IN+ dv/dt CLAMP GND_PWR CIRCUIT 1
-+
-+
V+(1, 2, 3)
V+(4,5,6) SUBSTRATE 1 SUBSTRATE 2
-+
GND_IN-(1,2,3)
-+
GND_IN-(4, 5, 6)
GND_PWR (1,2,3) ~1M ~1M GND(4, 5, 6)
-+
GND_PWR(1,2,3) CIRCUIT 4
1.5k
GND_PWR(4, 5, 6) CIRCUIT 5
-+ 1.5k
500
500
THERMAL HEAT SINK PAD CIRCUIT 6
2
FN6640.1 September 11, 2008
ISL55036
Absolute Maximum Ratings (TA = +25C)
Supply Voltage from V+ to GND . . . . . . . . . . . . . . . . . . . . . . . 5.75V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/s EN Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . V+ + 0.3V to GND - 0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3,000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 24 Ld TQFN Package . . . . . . . . . . . . . . . . . . . . . . . 42 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
V+ = 5V, TA = +25C, RL = 1k to V+/2, AV = 4, VIN = 0.1VDC, Unless Otherwise Specified. CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT
DESCRIPTION
INPUT CHARACTERISTICS TCVOS IB RIN CIN Offset Voltage Temperature Coefficient Input Bias Current Input Resistance Input Capacitance Measured from -40C to +85C VIN = 0V -10 -3 -5.5 7 0.5 -2.5 V/C A M pF
OUTPUT CHARACTERISTICS VOS ACL ROUT VOP Output Offset Voltage Closed Loop Gain Output Resistance Positive Output Voltage Swing Note 2 RL = 1k, 150, VOUT = 0.5V to 4V AV = +4 RL = 1k to 2.5V RL = 150 to 2.5V VON Negative Output Voltage Swing RL = 1k to 2.5V RL = 150 to 2.5V ISC (source) ISC (sink) Output Short Circuit Current Output Short Circuit Current RL = 10 to GND, VIN = 1.5V RL = 10 to + 2.5V, VIN = 0V 60 70 -14 3.9 -2 4 30 4.86 4.65 27 140 95 105 10 4.1 mV V/V m V V mV mV mA mA
POWER SUPPLY PSRR IS-ON IS-OFF ENABLE tEN tDS VIH-ENB VIL-ENB Enable Time Disable Time ENABLE Pin Voltage for Power-Up ENABLE Pin Voltage for Shut-Down RL = 150, VIN = 0.25V RL = 150, VIN = 0.25V 250 25 0.8 2 ns ns V V Power Supply Rejection Ratio @ 1kHz Supply Current - Enabled per Amplifier V+ = 5V; VSOURCE = 1VP-P; f = 1kHz sine wave RL = Open 6.0 0.5 78 7.2 1.1 8.5 2 dB mA mA
Supply Current - All Amplifiers Disabled RL = Open
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FN6640.1 September 11, 2008
ISL55036
Electrical Specifications
PARAMETER IIH-ENB IIL-ENB V+ = 5V, TA = +25C, RL = 1k to V+/2, AV = 4, VIN = 0.1VDC, Unless Otherwise Specified. (Continued) CONDITIONS VEN = 5V VEN = 0V MIN (Note 3) 1 -4 TYP 5.5 MAX (Note 3) 20 4 UNIT A A
DESCRIPTION ENABLE Pin Input Current High ENABLE Pin Input for Current Low
AC PERFORMANCE BW BW Peak dG dP eN-OUT iN ISO X-TALK -3dB Bandwidth 0.1dB Bandwidth Peaking Differential Gain Differential Phase Output Noise Voltage Input Noise Current Off-State Isolation fO = 10MHz Die to Die Crosstalk fO = 10MHz Same Die Channel-to-Channel Crosstalk, fO = 10MHz PSRR Power Supply Rejection Ratio fO = 10MHz VSOURCE = 1VP-P, CL = 3pF, RL = 150 RL = 150, CL = 3pF RL = 150, CL = 3pF RL = 150, CL = 3pF VIN = 0.1V to 1.0V, VOUT = 100mVP-P, f = 3.58MHz, RL = 150 f = 10kHz f = 10kHz VIN = 0.6VDC + 1VP-P, CL = 3pF, RL = 150 VIN = 0.6VDC + 1VP-P, CL = 3pF, RL = 150 400 40 1 0.06 0.01 50 0.9 -100 -85 -65 -55 MHz MHz dB % nV/Hz pA/Hz dB dB dB dB
TRANSIENT RESPONSE SR tr, tf Large Signal Slew Rate 25% to 75% Rise Time, tr 20% to 80% Fall Time, tf 20% to 80% Rise Time, tr 20% to 80% Fall Time, tf 20% to 80% tr, tf, Small Signal OS tPD tS tEN Rise Time, tr 20% to 80% Fall Time, tf 20% to 80% Overshoot Propagation Delay 1% Settling Time ENABLE to Output Turn-on Delay Time; 10% EN - 10% VOUT 200mV step 200mV step 2V step VOUT = 1VDC, RL = 150, CL = 3pF VOUT = 0.2VP-P, RL = 150, CL = 3pF VOUT = 2VP-P, RL = 150, CL = 3pF RL = 150, VOUT = 0.5V to 4.5V VOUT = 4VP-P, RL = 150, CL = 3pF 2500 1.4 1 0.8 0.7 0.75 0.7 5 0.6 12 250 25 V/s ns ns ns ns ns ns % ns ns ns ns
ENABLE to Output Turn-off Delay Time; VOUT = 1VDC, RL = 150, CL = 3pF 10% EN - 10% VOUT NOTES: 2. VOS is extrapolated from 2 output voltage measurements, with VIN = 62.5mV and VIN = 125mV, RL = 1k.
3. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
4
FN6640.1 September 11, 2008
ISL55036 Typical Performance Curves
6 5 NORMALIZED GAIN (dB) 4 3 -2 -1 0 -1 -2 -3 -4 V+ = 5V AV = +4 CL = 3pF VOUT = 100mVP-P 1M RL = 1k NORMALIZED GAIN (dB) RL = 499 5 4 3 2 1 0 -1 -2 -3 -4 V+ = 5V AV = +4 -5 RL = 150 -6 VOUT = 100mVP-P -7 100k 1M CL = 5.2pF CL = 3.0pF CL = 11.2pF CL = 7.7pF
RL = 150 RL = 100 10M 100M 1G
-5 100k
10M FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS RLOAD
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS CLOAD
1 0 NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 V+ = 5V AV = +4 RL = 150 CL = 3pF 1M 100M 10M FREQUENCY (Hz) 1G VOUT = 4VP-P VOUT = 3VP-P VOUT = 100mVP-P VOUT = 1VP-P VOUT = 2VP-P GAIN (dB)
15 14 13 12 11 10 9 8 7 6 V+ = 5V AV = +4 RL = 150 CL = 3pF VOUT = 100mVP-P 100k 1M 10M 100M 1G ALL CHANNELS
-9 100k
5 10k
FREQUENCY (Hz)
FIGURE 4. -3dB BANDWIDTH vs VOUT
FIGURE 5. GAIN vs FREQUENCY - ALL CHANNELS
0.2 0.1 NORMALIZED GAIN (dB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 10k V+ = 5V AV = +4 RL = 150 CL = 3pF VOUT = 100mVP-P 100k 1M FREQUENCY (Hz) 10M 100M PSRR (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 1k 10k 100k 1M 10M 100M V+ = 5V AV = +4 RL = 150 CL = 3pF VSOURCE = 1VP- P ALL INPUTS = +0.2V DC
FREQUENCY (Hz)
FIGURE 6. 0.1 dB GAIN FLATNESS
FIGURE 7. PSRR vs FREQUENCY
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FN6640.1 September 11, 2008
ISL55036 Typical Performance Curves
0 -20 OFF ISOLATION (dB) -40 -60 -80 -100 -120 10k V+ = 5V AV = +4 RL = 150 CL = 3pF VIN = 0.6VDC+1VP-P ALL INPUTS = +0.6VDC
(Continued)
V+ = 5V AV = +4 -20 RL = 150 CL = 3pF CHANNEL) = 4VPVOUT (DRIVEN CHANNEL) = 4VP-P -40 P ALL INPUTS = +0.6V DC -60 CHANNELS ON SAME DIE -80 -100 CHANNELS ON DIFFERENT DIE -120 10k 0
OFF ISOLATION (dB)
100k
1M 10M FREQUENCY (Hz)
100M
1G
100k
1M 10M FREQUENCY (Hz)
100M
1G
FIGURE 8. OFF ISOLATION vs FREQUENCY
FIGURE 9. CHANNEL-TO-CHANNEL CROSSTALK vs FREQUENCY
10000 OUTPUT VOLTAGE NOISE (nV/Hz) INPUT CURRENT NOISE (pA/Hz)
100.0
1000
10.0
100
1.0
10 1
10
100
1k
10k
100k
1M
10M
0.1 1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 10. OUTPUT NOISE VOLTAGE vs FREQUENCY
FIGURE 11. INPUT REFERRED NOISE CURRENT vs FREQUENCY
5.5 5.0 4.5 4.0 ENABLE (V) 3.5 3.0 2.5 2.0 V+ = 5V AV = +4 1.5 RL = 150 1.0 CL = 3pF 0.5 VIN = 0.25V 0 -0.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VOUT DISABLE
1.8 1.5 SMALL SIGNAL (V) 1.2 0.9 0.6 ENABLE 0.3 0 2.0
0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 V+ = 5V AV = +4 RL = 150 CL = 3.0pF VOUT = 250mVP-P
OUTPUT (V)
0
5
10
15
20
25
30
35
40
45
50
TIME (s)
TIME (ns)
FIGURE 12. ENABLE/DISABLE TIMING
FIGURE 13. SMALL SIGNAL STEP RESPONSE
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FN6640.1 September 11, 2008
ISL55036 Typical Performance Curves
3.0 2.5 3.5 SMALL SIGNAL (V) LARGE SIGNAL (V) 2.0 1.5 1.0 0.5 0.5 0 0 5 10 15 20 25 30 35 40 45 50 0 0 5 10 15 20 25 30 35 40 45 50 V+ = 5V AV = +4 RL = 150 CL = 3.0pF VOUT = 2VP-P 3.0 2.5 2.0 1.5 1.0 V+ = 5V AV = +4 RL = 150 CL = 3.0pF VOUT = 4VP-P
(Continued)
4.5 4.0
TIME (ns)
TIME (ns)
FIGURE 14. SMALL SIGNAL (2VP-P) STEP RESPONSE
FIGURE 15. LARGE SIGNAL (4VP-P) STEP RESPONSE
0.004 0.002 NORMALIZED GAIN (dB) NORMALIZED PHASE () 0 -0.002 -0.004 -0.006 -0.008 -0.010 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 INPUT DC OFFSET (V) V+ = 5V AV = +4 RL = 150 CL = 3pF
0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 V+ = 5V AV = +4 RL = 150 CL = 3pF
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 INPUT DC OFFSET (V)
FIGURE 16. DIFFERENTIAL GAIN
FIGURE 17. DIFFERENTIAL PHASE
100k
10k ZIN () 1k
V+ = 5V AV = +4 RL = 150 CL = 3.0pF VSOURCE = 100mVP-P 1M 10M FREQUENCY (Hz) 100M 1G
100 100k
FIGURE 18. ZIN vs FREQUENCY
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FN6640.1 September 11, 2008
ISL55036 Typical Performance Curves
100.00 V+ = 5V AV = +4 RL = 150 CL = 3.0pF VSOURCE = 100mVP-P
(Continued)
10k
ZOUT ENABLED ()
ZOUT DISABLED ()
10.00
1k
1.00
100
0.10
V+ = 5V AV = +4 RL = 150 CL = 3.0pF VSOURCE = 100mVP-P 1M 10M 100M FREQUENCY (Hz) 1G
0.01 100k
1M
10M 100M FREQUENCY (Hz)
1G
10 100k
FIGURE 19. ZOUT (ENABLED) vs FREQUENCY
FIGURE 20. ZOUT (DISABLED) vs FREQUENCY
7.8 CURRENT PER AMPLIFIER (mA) n = 100 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0 -40 -20 0 20 40 60 80 MIN MEDIAN CURRENT (mA) MAX
1.21 n = 100 1.16 MAX
1.11
MEDIAN
1.06 MIN 1.01
0.96 -40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 21. ENABLED SUPPLY CURRENT vs TEMPERATURE, VS = 2.5V
FIGURE 22. DISABLED SUPPLY CURRENT vs TEMPERATURE, VS = 2.5V
6 OUTPUT OFFSET VOLTAGE VOS (V) n = 100 4 2 IBIAS (A) 0 -2 -4 -6 -8 -40 MEDIAN MAX
-4.7 -4.9 -5.1 -5.3 -5.5 -5.7 -5.9 -6.1 MIN -6.3 -6.5 -20 0 20 40 60 80 -6.7 -40 -20 0 20 40 60 80 MIN MEDIAN n = 100 MAX
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 23. OUTPUT OFFSET VOLTAGE VOS vs TEMPERATURE, VS = 2.5V, RL = 1k
FIGURE 24. IBIAS vs TEMPERATURE, VS = 2.5V
8
FN6640.1 September 11, 2008
ISL55036 Typical Performance Curves
(Continued)
120 115 n = 100 110 PSRR (dB) 105 100 95 90 85 80 -40 -20 0 20 MIN MEDIAN MAX
40
60
80
TEMPERATURE (C)
FIGURE 25. PSRR vs TEMPERATURE 4.5V TO 5.5V
Application Information
General
The ISL55036 single supply, fixed gain hex amplifier is well suited for a variety of video applications. The device features a PNP ground-sensing input stage and a bipolar rail-to-rail output stage. The ISL55036 is designed for general purpose video, communication, instrumentation, and industrial applications. The 6 fixed gain amplifiers operate independently, however, they are organized into 2 triple amplifier groups as shown in Figure 26. Each group has its own set of power supply pins, ground pins, enable-disable logic and input ground reference pins.
clamp imposes a maximum supply turn-on slew rate of 1V/s. Damaging currents can flow for power supply rates-of-rise in excess of 1V/s, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the maximum rate of rise is not exceeded.
EN and Power-Down States
The EN pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the EN pin. The power-down state is established within approximately 25ns, if a logic high (>2V) is placed on the EN pin. In the power-down state, supply current is reduced significantly by shutting the three amplifiers off. The output presents a relatively high impedance (~2k) to the output pin. Multiplexing several outputs together is possible using the enable/disable function as long as the application can tolerate the limited power-down output impedance.
Ground Connections
For the best isolation performance and crosstalk rejection, all GND pins must connect directly to the GND plane. In addition, the electrically conductive thermal pad should also connect directly to ground.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 40mA. Adequate thermal heat sinking of the parts is also required.
Power Considerations
Each triple amplifier group has its own power supply and ground pins. There are dedicated V+ OUT and GND VOUT pins to power only the output stage. A separate set of power and ground pins power the rest of each of the triple op amps (V+ and PWR GND). Providing separate power pins provides a way to prevent high speed transient currents in the output stage from bleeding into the sensitive amplifier input and gain stages. To maximize crosstalk isolation, each power supply pin should have its own de-coupling capacitors connected as close to the pin as possible (0.1F in parallel with 1nF recommended). The ESD protection circuits use internal diodes from all pins to the V+ and ground pins. In addition, a dv/dt-triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 on page 2. The dv/dt triggered
PC Board Layout
The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * The use of low inductance components, such as chip resistors and chip capacitors, is strongly recommended. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners. Use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be
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FN6640.1 September 11, 2008
ISL55036
DECOUPLING CAPACITORS
EN(1,2,3)
V+(1,2,3) V+_OUT(1,2,3) GND_OUT(4,5,6) -+
IN+_1 IN+_2 IN+_3 RIN 4 RIN 5
ROUT 1 ROUT 2 ROUT 3 GND_PWR(1,2,3) V+ (4,5,6) V+_OUT(4,5,6) GND_OUT(4,5,6)
OUT_1 OUT_2 OUT_3
RIN 6 GND_IN(1,2,3)
DIE 1 DECOUPLING CAPACITORS
-+
IN+_4 IN+_5 IN+_6 RIN 6 RIN 4 RIN 5
-+
-+
ROUT 4 ROUT 5 ROUT 6 GND_PWR(4,5,6)
OUT_4 OUT_5 OUT_6
DIE 2 GND_IN(4,5,6)
EN(4,5,6)
FIGURE 26. BASIC APPLICATION CIRCUIT
degraded for traces greater than one inch, unless controlled impedance (50 or 75) strip lines or microstrips are used. * Match channel-to-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. * Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. * When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * A minimum of 2 power supply decoupling capacitors are recommended (1000pF, 0.01F) as close to the devices as possible. Avoid vias between the capacitor and the device because vias add unwanted inductance. Larger capacitors
-+
-+
can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. * The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk.
The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad
The thermal pad is electrically connected to power supply ground through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the power ground pins through the substrate, the thermal pad must be tied to the power supply ground to prevent unwanted current flow through the thermal pad. Maximum AC performance is achieved if the thermal pad has good contact to the IC ground pins. Heat sinking requirements can be satisfied using thermal vias directly beneath the thermal pad to a heat dissipating layer of a square at least 1" on a side.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN6640.1 September 11, 2008
ISL55036
Package Outline Drawing
L24.4x5C
24 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 10/07
PIN 1 INDEX AREA 6 B 20 24 4.00 A 2.65
24X0.40
PIN #1 INDEX AREA CHAMFER 0.400 X 45 x 6 1 0.50
19
5.00
3.65
0.5x6=3.00 REF
13
7
0.10
12 0.50
8 0.230.05 0.10 M C A B
4X
TOP VIEW
0.5x4=2.00 REF
BOTTOM VIEW
SEE DETAIL X'' 0.10 C C 0.75 (24x0.25) SIDE VIEW (4.80 TYP) (3.65) SEATING PLANE 0.08 C
(20x0.50) 5
0 . 20 REF
C (24x0.60) (2.65) (3.80 TYP) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"
NOTES:
1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.28mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
11
FN6640.1 September 11, 2008

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